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nios2

Here are 33 public repositories matching this topic...

SweetAda

gabriele-galeotti / SweetAda

Ada-language framework

Updated Nov 24, 2024
Ada

Goshik92 / multicore-nios

Matrix multiplication on multiple Nios II cores

fpga parallel-computing matrix-multiplication verilog mailbox nios shared-memory hdl fpga-soc qsys parallel-programming nios2 de2-115 quartus spmd sopc platform-designer

Updated Feb 12, 2020
C

MinatsuT / CYC1000_SDRAM

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

fpga quartus-prime nios2 sdram sdram-controller cyclone-10lp cyc1000

Updated Jul 8, 2021
Verilog

kimushu / tinythreads

POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000

zynq posix pic32 mips32 nios2 zynq-7000

Updated Jun 14, 2020
C

timot3 / ECE385-Ethernet

ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

fpga ethernet ethernet-shield nios2 de10-lite nios-ii

Updated Dec 13, 2021
Verilog

electro-logic / CameraVision2

Connect a modern, high-resolution camera to an FPGA and easily develop your applications

Updated Jul 19, 2024
C

Nathen-Smith / FPGA-super-mario-bros

FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

systemverilog fpga-soc quartus-prime nios2

Updated Dec 16, 2021
Verilog

vacer25 / Nios_II-VGA-Out

Various VGA video output projects on the NIOS II processor

interactive assembly vga nios2 vga-frame-buffer vga-screen nios-ii

Updated Sep 22, 2018
Assembly

fbponz / Terasic-DE2-115-NiosII-uCosII

Design for board DE2-115, microprocessor soft running a uCOS-II(Real Time Operating System). Application to test is a Lift program

real-time rtos qsys nios2 de2-115 ucos-ii quartus niosii-ucosii

Updated Mar 18, 2017
Verilog

samdejong86 / Arria-V-ADC-Ethernet

Transfers data from an ADC to a PC via ethernet

socket telnet vhdl verilog adc ethernet nios2 quartus altera-fpga arria-v

Updated Jun 7, 2018
Verilog

sickRanchez-c137 / InferenceInFPGA

A Deep Neural Network-inference accelerator is created in hardware. The codes for hardware is written in System Verilog. The hardware module is interfaced with NIOS computer system, thus this hardware acts as a peripheral to the computer system. The driver code to interface the hardware is written in C. Speedup compard to software is 400 times.

arm deep-learning systemverilog hardware-acceleration nios2 inference-engine

Updated Nov 18, 2020
SystemVerilog

montao / nios2-mmu

Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.

altera hardware-designs mmu quartus-prime nios2

Updated Apr 13, 2017
Verilog

jimfangx / DE2-70-Bringup

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

fpga verilog ethernet altera modelsim vga nios2 vga-controller quartus2 terasic de2-70

Updated Jun 26, 2024
C

vaddya / hdl

Hardware Description Languages

verilog systemverilog modelsim qsys nios2 quartus hardware-description-language

Updated Jan 7, 2019
C

joe-el-khoury / brobot-compiler

A compiler for a custom made language to control robots.

language compiler assembly assembly-language-programming nios2

Updated Dec 18, 2016
Assembly

bchampp / altera-nios-II

Code from FPGA programming with the Altera Nios II

assembly microprocessor nios2

Updated Apr 23, 2020
C

mcquerol / fsoc-sha1-niosii-implementation

SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.

c fpga sha1 systemverilog nios2 softcore register-programming cyclone-5

Updated Aug 23, 2024
C

SakaSerbia / FPGA-DE10-Standard-Simple-Nios2-Project

Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.

fpga basic-learning verilog fpga-soc qsys nios2 nios-ii fpga-programming

Updated Aug 19, 2021
Verilog

Insper / Embarcados-Avancados

SoC and Embedded Linux

education arm fpga-soc embedded-linux nios2 intel-fpga hps de10-standard computer-engineer

Updated Nov 22, 2024
JavaScript

KelvinThomasYB17 / VGA-Radar-sensor-using-VHDL-and-NIOS-II

KelvinThomasYB17/VGA-Radar-sensor-using-VHDL-and-NIOS II

fpga radar vhdl hc-sr04 fpga-soc vga nios2 de10-lite nios-ii hc-sr04-ultrasonic-sensor

Updated Oct 7, 2024
VHDL

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